Design aspects of dual gate GaAs nanowire FET for room temperature charge qubit operation: A study on diameter and gate engineering

The current work explores a geometrically engineered dual gate GaAs nanowire FET with state of the art miniaturized dimensions for high performance charge qubit operation at room temperature. Relevant gate voltages in such device can create two voltage tunable quantum dots (VTQDs) underneath the gates, as well as can manipulate their eigenstate detuning and the inter-dot coupling to generate superposition, whereas a small drain bias may cause its collapse leading to qubit read out. Such qubit operations, i.e., Initialization, Manipulation, and Measurement, are theoretically modeled in the present work by developing a second quantization filed operator based Schrodinger-Poisson self-consistent framework coupled to non-equilibrium Greens function formalism. The study shows that the Bloch sphere coverage can be discretized along polar and azimuthal directions by reducing the nanowire diameter and increasing the inter-dot separation respectively, that can be utilized for selective information encoding. The theoretically obtained stability diagrams suggest that downscaled nanowire diameter and increased gate separation sharpen the bonding and anti-bonding states with reduced anticrossing leading to a gradual transformation of the hyperbolic current mapping into a pair of straight lines. However, the dephasing time in the proposed GaAs VTQD-based qubit may be significantly improved by scaling down both the nanowire diameter and gate separation. Therefore, the present study suggests an optimization window for geometrical engineering of a dual gate nanowire FET qubit to achieve superior qubit performance. Most importantly, such device is compatible with the mainstream CMOS technology and can be utilized for large scale implementation by little modification of the state of the art fabrication processes

Characterization of epitaxial GaAs MOS capacitors using atomic layer-deposited TiO2/Al2O3 gate stack: study of Ge auto-doping and p-type Zn doping

Electrical and physical properties of a metal-oxide-semiconductor [MOS] structure using atomic layer-deposited high-k dielectrics (TiO2/Al2O3) and epitaxial GaAs [epi-GaAs] grown on Ge(100) substrates have been investigated. The epi-GaAs, either undoped or Zn-doped, was grown using metal-organic chemical vapor deposition method at 620°C to 650°C. The diffusion of Ge atoms into epi-GaAs resulted in auto-doping, and therefore, an n-MOS behavior was observed for undoped and Zn-doped epi-GaAs with the doping concentration up to approximately 1017 cm-3. This is attributed to the diffusion of a significant amount of Ge atoms from the Ge substrate as confirmed by the simulation using SILVACO software and also from the secondary ion mass spectrometry analyses. The Zn-doped epi-GaAs with a doping concentration of approximately 1018 cm-3 converts the epi-GaAs layer into p-type since the Zn doping is relatively higher than the out-diffused Ge concentration. The capacitance-voltage characteristics show similar frequency dispersion and leakage current for n-type and p-type epi-GaAs layers with very low hysteresis voltage (approximately 10 mV)

Analytical modeling of the lattice and thermo-elastic coefficient mismatch-induced stress into silicon nanowires horizontally embedded on insulator-on-silicon substrates

International audienceIn the current work, an analytical model has been developed to estimate the amount of induced stress in nanowires which are horizontally embedded with different fractions within an Insulator-on-Silicon substrate. For estimating such stress, different crystallographic orientations of substrates and embedded nanowires have been considered. The induced stress for both the difference in thermo-elastic constants and lattice-mismatch is included and accuracy of the analytical model has been verified with the similar results obtained from ANSYS Multiphysics. Induced stress is observed to be insensitive of the nanowire size, however, depends significantly on the fractional insertion of the nanowires. A tensile stress of 1.95 GPa and a compressive stress of -1.0719 GPa have been obtained for the 〈100〉 oriented Si-nanowires. Hole mobility of 850 cm2/Vs can be achieved for the 3/4th insertion of the nanowires which is comparable to electron mobility and therefore can be utilized for the design of symmetric nano-electronic devices

Progress in VLSI Design and Test16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings /

XXIV, 408 p. 275 illus.online resource

ANGULAR-DEPENDENCE OF SECONDARY-ELECTRON FINE-STRUCTURE IN AUGER-ELECTRON SPECTRA

In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has been given on the evaluation of noise characteristics and low-power performance along with the delay characteristics under different channel straining conditions. An inverter circuit has been used for performance evaluation through simulation where the device simulator is calibrated with experimental device data. The result shows a great promise for s-Si technology in digital applications which require high throughput and low power